Mixed ASIC/FPGA and software design and simulation using Verilator

Gregory Estrade

Thématique
Open Hardware & Embarqué
Niveau
Intermédiaire
Horaire
samedi 15 nov, 16:30 – 17:00
Salle
A202 - OpenHardware & embarqué

Description

Verilator is a Verilog HDL simulator that generates optimized C++ models of your hardware design. Learn how to use it to write testbenches, then perform both software and hardware validation of your models, and benefit from the best of both worlds.

Description détaillée

Verilator Unleashed

Programme

  • "Verilation" d'un SoC de test.
  • Simulation du SoC, 100% Verilog.
  • Ajout de traces (VCD).
  • Simulation du SoC, avec parties en C++.
  • Intégration du désassembleur 68000 de Musashi.
  • Simulation et vérification conjointe avec Musashi.

Medias

Intervenant(es)

Gregory Estrade

Gregory Estrade

Gregory Estrade

General

French, male, born on 1973-11-14.

@Torlus on Twitter.

Graduated from ENSEIRB, CS Department, specialized in Parallel and Distributed Applications.

Work Experience

Since 2003, Software engineer, and now Development Director at Lyra Network, a financial transactions processor and network operator.

Projects

See them on GitHub

Software

  • Raspberry Pi support for QEMU

Hardware

  • Many FPGA projects, mostly about retro-gaming and retro-computing (hardware emulation)
  • Electronics add-on for legacy devices.

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